Further reductions in VLSI CMOS geometries require commensurate reduction in the thickness of the gate oxide layer. Because the quality and predictability of the gate oxide tends to degrade as the thickness of the oxide layer is reduced, improvements over existing gate oxide processes are necessary in the effort to achieve and penetrate the one micron milestone CMOS geometry.
Breakdown voltage and leakage current are among the device characteristics critically dependent on the gate oxide thickness. Breakdown voltage may be defined as the voltage, applied between the gate and substrate, required to produce a specified current flow, typically 10 microamperes, through the gate oxide. It may be viewed as a measure of the effectiveness of the oxide as a dielectric. Leakage current is generally defined as the current flowing through the oxide layer as a result of a gate-to-substrate voltage, typically 5 volts, less than the breakdown voltage.
Although the consistency of breakdown voltage measurement data degrades with reductions in the gate oxide thickness encountered, it is known that the average breakdown voltage decreases with decreasing oxide thickness. Leakage current, on the other hand, has been found to increase dramatically with decreasing gate oxide thickness. For example, 1.2 micron CMOS devices fabricated according to a process not benefitted by the subject invention have yielded leakage current measurements beyond the 10 microampere value. Furthermore, breakdown voltage measurements on such devices have produced values of approximately 20 volts, at a standard deviation in excess of 4 volts. Target requirements for the 1.2 micron devices had been 20 volts minimum breakdown voltage and 1 nanoampere leakage current at 5 volts.
An additional requirement of fine geometry CMOS devices is low surface state charge. Surface state charge may be empirically determined from the well known theoretical equation for the threshold voltage of a MOS device. The determination may be derived from CV (i.e., capacitance - voltage) measurements performed on the device using commercially available test equipment. For the device geometries alluded to above, the requirement corresponds to a flat band voltage shift in a C-V plot, of less than 0.1 volt at a temperature bias of 300 degrees Centigrade. Satisfaction of this requirement is deemed largely problematic without resort to the invention disclosed herein.